Search - SINE WAVE VHDL

[VHDL-FPGA-Verilog] 用modelsim仿真一个正弦波产生程序

Description: 用modelsim仿真一个正弦波产生程序-modelsim simulation using a sine wave generated procedures
Platform: | Size: 68608 | Author: 阿乐 | Hits:

[VHDL-FPGA-Verilog] sinewave

Description: 6通道正弦波发生器，产生频率，相位，幅值都可调的正弦波形-6-channel sine wave generator, resulting in frequency, phase, amplitude of the sinusoidal waveform are adjustable
Platform: | Size: 1024 | Author: 桑武斌 | Hits:

[assembly language] sine

Description: 用verilog语言编的正弦波发生器，可以用QuartusII来打开这个源码，也可以转换成VHDL语言-Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language
Platform: | Size: 104448 | Author: 雨孩 | Hits:

[Algorithm] VHDL

Description: 此代码可产生正弦波、三角波、正斜率拨、负斜率波波、矩形波五种波形-This code can generate sine wave, triangle wave, the slope is allocated, the negative slope of the ball, five rectangular-wave waveform
Platform: | Size: 1024 | Author: 刘三平 | Hits:

[VHDL-FPGA-Verilog] sin_generator

Description: 在quartus 11 5.1 里用VHDL编写的正弦波发生器，经过仿真通过-Quartus 11 5.1 years in VHDL prepared using sine wave generator, through simulation through
Platform: | Size: 245760 | Author: 郭翠双 | Hits:

[SCM] wave-generator

Description: 产生方波，三角波，正弦波，余弦波等波形，并且可以自由选择和切换，最后可以用于波形输出-Have a square wave, triangle wave, sine wave, cosine wave, such as waveform, and can freely choose and switch, and finally can be used for waveform output
Platform: | Size: 6144 | Author: 周易 | Hits:

[VHDL-FPGA-Verilog] sine

Description: chdl 64位计数器，利用mif格式文件产生正弦波。可以在fpga模拟正弦波-chdl 64 bit counter, using sine wave generated mif format. Sine wave can be simulated in FPGA
Platform: | Size: 268288 | Author: yyqdian | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于Quartus II 5.0编写的正弦波发生器，可控频率，用vhdl编写的-Quartus II 5.0 on the preparation of the sine wave generator, controllable frequency, prepared using VHDL
Platform: | Size: 475136 | Author: uuk | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于fpga的正弦波发生器设计，有一定的参考价值，写的比较详细-The sine wave generator based on FPGA design, have a certain reference value, a more detailed written
Platform: | Size: 632832 | Author: qlg | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成各种波形的线形叠加输出。 -Realize four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency, magnitude controllable output (square wave A, is also a controllable duty cycle), can store arbitrary waveform feature data and can reproduce the waveform, but also completed a variety of linear superposition of the output waveform.
Platform: | Size: 9216 | Author: zhanyi | Hits:

[VHDL-FPGA-Verilog] sine-generator

Description: 原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成，可产生正弦波。更改rom内容可改变波形-Original: Using VHDL languages sinusoidal signal generator. rom using Quartus LPM s own generation, can produce sine wave. Rom content changes can change the waveform
Platform: | Size: 675840 | Author: zzwuyu | Hits:

[VHDL-FPGA-Verilog] sin125

Description: 用FPGA实现DDS的信号发生器（正弦波125kHz）-Using FPGA to achieve DDS signal generator (sine wave 125kHz)
Platform: | Size: 196608 | Author: 杜海明 | Hits:

[VHDL-FPGA-Verilog] VHDL-ROM4

Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Platform: | Size: 98304 | Author: 宫逢源 | Hits:

[Other] bxfsq

Description: 波形发生器的代码，具有产生正弦波、方波、三角波的功能。-Waveform Generator code has generated sine wave, square, triangle-wave function.
Platform: | Size: 16384 | Author: 李仁刚 | Hits:

[VHDL-FPGA-Verilog] daout-Sine-wave

Description: 正弦波的vhdl输出，使用VHDL编写的，已经通过调试-Sine wave output of the VHDL, the use of VHDL prepared already through debugging
Platform: | Size: 585728 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] signal_generator

Description: 基于vhdl的多功能函数信号发生器的设计，能实现三角波、方波、正弦波。-VHDL-based multi-function signal generator design, can achieve the triangular wave, square wave, sine wave.
Platform: | Size: 1024 | Author: tony | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: DDS产生正弦波（VHDL语言）用DDS产生3MHZ的正弦波,VHDL控制语言-DDS have a sine wave (VHDL language) 3MHZ generated by the DDS sine wave, VHDL control language
Platform: | Size: 1024 | Author: chenyubin | Hits:

[Software Engineering] DDS

Description: 本设计基于数字频率合成技术,采用正弦查找表实现波形产生.直接数字频率合成技术（DDS）是一种先进的电路结构，能在全数字下对输出信号频率进行精确而快速的控制，DDS技术还在解决输出信号频率增量选择方面具有很好的应用，DDS所产生的信号具有频率分辨率高、频率切换速度快、频率切换时相位连续、输出相位噪声低和可以产生任意波形等诸多优点。文中介绍了DDS的基本原理，对DDS的质谱及其散杂抑制进行了分析。程序设计采用超高速硬件描述语言VHDL描述DDS,在此基础上设计了正弦波、三角波、方波等信号发生器，。完成了软件和硬件的设计，以及实验样机的部分调试。 -The design is based on a digital frequency synthesis technology, to achieve wave synthesis by sine wave look-up tables. Direct Digital Synthesis Technology (DDS) is an advanced circuit structure, the output signal frequency is controlled precisely and rapidly in all-digital process, DDS technology has been applied in output signal frequency increment. DDS signals generated own high frequency resolution, frequency switching speed and continuous phase when frequency switching, low-output phase noise and can generate arbitrary waveform, and so on. Basic principles of the DDS is introduced in the paper, frequency form and stray inhabitation of the DDS is analyzed. Procedures designed with high-speed hardware description language VHDL describe DDS, and design a sine wave, triangle wave, square-wave signal generator by it.The hardware and software has been designed, prototype and circuit has been tested partly.
Platform: | Size: 312320 | Author: 蓝 | Hits:

[Embeded Linux] 83390078DDS

Description: DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器（LPF）。频率累加器对输入信号进行累加运算，产生频率控制数据X（frequency data或相位步进量）。相位累加器由N位全加器和N位累加寄存器级联而成，对代表频率的2进制码进行累加运算，是典型的反馈电路，产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器，以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works the way we are digitally controlled oscillator frequency, phase controlled sine wave. Circuits generally include reference clock, frequency accumulator, phase accumulator, amplitude/phase converter circuit, D/A converter and low-pass filter (LPF). The frequency accumulator to accumulate the input signal operation to produce the frequency control data X (frequency data or phase stepping volume). From the N-bit phase accumulator and the N-bit full adder cascade accumulation register is made on behalf of the frequency of the two binary codes accumulation operation, is a typical feedback circuit, resulting in cumulative results of Y. Amplitude/phase converter circuit is essentially a waveform register for look-up table to use. Read out the data into the D/A converter and low pass filter.
Platform: | Size: 44032 | Author: 394177191 | Hits:

[VHDL-FPGA-Verilog] VHDL(sin)

Description: 基于ROM的正弦波发生器的设计一．实验目的 1. 学习VHDL的综合设计应用 2. 学习基于ROM的正弦波发生器的设计二．实验内容设计基于ROM的正弦波发生器，对其编译，仿真。具体要求： 1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based sine wave generator design 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning ROM-based sine wave generator design 2. Experimental content ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB. 3. The 50MHz input clock.
Platform: | Size: 17408 | Author: 爱好 | Hits:

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[VHDL-FPGA-Verilog] 用modelsim仿真一个正弦波产生程序

[VHDL-FPGA-Verilog] sinewave

[assembly language] sine

[Algorithm] VHDL

[VHDL-FPGA-Verilog] sin_generator

[SCM] wave-generator

[VHDL-FPGA-Verilog] sine

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] sine-generator

[VHDL-FPGA-Verilog] sin125

[VHDL-FPGA-Verilog] VHDL-ROM4

[Other] bxfsq

[VHDL-FPGA-Verilog] daout-Sine-wave

[VHDL-FPGA-Verilog] signal_generator

[VHDL-FPGA-Verilog] VHDL

[Software Engineering] DDS

[Embeded Linux] 83390078DDS

[VHDL-FPGA-Verilog] VHDL(sin)

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